AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

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Document Table of Contents Block-Based Design Flow

In the Vivado* software, the Hierarchical Design flow allows you to partition a design into smaller modules that you process independently. These flows are based on the ability to implement a partitioned module out-of-context (OOC) from the rest of the design. A similar feature in Intel® Quartus® Prime Pro Edition software is the Block-Based Design Flow, which supports preservation and reuse of design blocks in one or more projects.

The Block-Based Design Flow allows you to reuse synthesized or final design blocks within the same project, or export the block to other projects. Reusable design blocks can include device core or periphery resources.

You can define a logical design partition in a project, and then empty, preserve, or export the contents of that design partition after compilation. The Intel® Quartus® Prime Pro Edition software supports the following block-based design flows:

  • Incremental Block-Based Compilation—preserve or empty a core design partition within a project. This flow works only with core resources, and requires no additional files or floorplanning. You can empty the partition, or preserve it at synthesis, placement, or final compilation stages.
  • Design Block Reuse—export a core or periphery design partition and reuse it in another project. Core partition reuse preserves the placement and routing of timing-critical modules with specific optimized functionality or algorithms, such as modules for encryption, encoding, image processing, or other functions. Periphery partition reuse preserves the placement and routing of the periphery.
Table 39.  Block-Based Design Flows Comparison
AMD* Xilinx* Hierarchical Design Flows Intel® Quartus® Prime Pro Edition Block-Based Design Flows Description
Bottom-Up Reuse Design Block Reuse Build a verified module (such as a piece of IP) which is placed, routed and you can reuse in other designs.
Top-Down Reuse Periphery Reuse Build a verified top-level design with details about the pinout, floorplan and timing requirements.

For more information about design planning and different design approaches, refer to Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design.