AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents System Console

AMD* Xilinx* Vivado* software's Hardware Manager provides a TCL console to interact with the debug IP on the hardware. Similarly, in the Intel® Quartus® Prime software, you can perform the same tasks using the System Console.

Table 27.  System Console Features and Usage
Features Typical Usage
  • Provides real-time in-system debugging capabilities using available debugging toolkits.
  • Allows you to read from and write to memory mapped components in a system without a processor or additional software.
  • Communicates with hardware modules in a design through a Tcl interpreter.
  • Allows you to take advantage of all the features of the Tcl scripting language.
  • Supports JTAG and TCP/IP connectivity.
  • Perform system-level debugging.
  • Debug or optimize signal integrity of a board layout even before finishing the design.
  • Debug external memory interfaces.
  • Debug an Ethernet Intel FPGA IP interface in real time.
  • Debug a PCI Express* link at the Physical, Data Link, and Transaction layers.
  • Debug and optimize high-speed serial links in your board design.