AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

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4.3.4. Retimer Constraints

In the Intel® Quartus® Prime Pro Edition Software, the Fitter's Retime stage moves (retimes) existing registers into Hyper-Registers for fine-grained performance improvement (available in Intel® Stratix® 10 and Intel Agilex® 7 devices). AMD* Xilinx* devices do not have Hyper-Registers in their architecture, hence the existing Vivado* based designs do not have equivalent constraints.