AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

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Document Table of Contents

3.3. FPGA Design Flow Using Tools with GUIs

The Intel® Quartus® Prime Pro Edition and the Vivado* software GUIs address the major FPGA design steps in different ways.

Table 9.  GUI Feature Equivalents
GUI Feature AMD* Xilinx* Vivado* Software Intel® Quartus® Prime Pro Edition Software
Project Creation New Project New Project Wizard
Design Entry HDL Editor HDL Editor
EDA Netlist EDA Netlist
- Schematic/Block Editor
- State Machine Editor
- State Machine Viewer
IP Catalog IP Catalog and Parameter Editor
IP Integrator Platform Designer System Integration Tool
IP Packager Platform Designer Component Editor
IP Status Report IP Status Upgrade IP Components
Design Constraints Device, Physical and Timing Constraints window

Assignment Editor,

Timing Analyzer Text Editor

Synthesis Synthesis Analysis and Synthesis
Third-Party EDA Synthesis Third-Party EDA Synthesis
Design Implementation Implementation Fitter (Plan, Place, Route, Retime0 and Finalize)
Finalize Pinout

Byte Planner for memory banks

Device Window and Package Window in I/O Planning View Layout

Interface Planner

Tile Interface Planner

Pin Planner

Viewing and Editing Design Placement

Device Window (in I/O Planner View Layout)

Package Window (in I/O Planner View Layout)

Chip Planner
Static Timing Analysis Report Timing Timing Analyzer
Generation of Device Programming Files Hardware Manager Assembler
Power Analysis

AMD* Xilinx* Power Estimator (XPE)

Report Power

Power and Thermal Calculator (PTC)

Early Power Estimation (EPE)

Power Analyzer

Simulation Vivado* Simulator

Questa* Intel® FPGA Starter Edition

Third-Party Simulation Tools Third-Party Simulation Tools
Hardware verification Hardware Manager System Console
Integrated Logic Analyzer (ILA) and System ILA IP Signal Tap Logic Analyzer
AMD* Xilinx* Virtual Input Output (VIO) In-System Sources and Probes
JTAG-to-AXI Master System Console
IBERT IP and Serial I/O Analyzer Tool Transceiver Toolkit
Memory Calibration Debug Tool

EMIF Debug Toolkit


Remote Debug using AMD* Xilinx* Virtual Cable (XVC) Remote Debug using existing TCP/IP connection

Signal Probe

In-System Memory Content Editor

Logic Analyzer Interface (LAI)

View Netlist

Schematic Window (Elaborated)

Schematic Window (Synthesized)

Schematic Window (Implemented)

RTL Viewer (Post Synthesis)

Technology Map Viewer (Post-Mapping)

Technology Map Viewer (Post-Fitting)

Fast Forward Viewer (Post-Fitting)

Design Optimization - Hyper-Aware Design Flow10
Physical Optimization Physical Synthesis Optimization
Techniques to improve productivity Incremental Compile Block-Based Design Flows
Hierarchical Design
- Design Space Explorer II (DSE)
Design Rule Checking Design Assistant
Intermediate Design Snapshot Viewer
Partial Reconfiguration Yes Yes
Output Products Design Checkpoints Export Design Partitions
Add-On Development Tools Vivado* High-Level Synthesis High-Level Synthesis Compiler


10 Hyper-Aware Design Flow available only for Intel® Stratix® 10 devices.