AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

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Document Table of Contents Output Synchronous Set/Reset

AMD* Xilinx* memory supports optional synchronous set/reset pins that control the reset operation of the last register in the output stage. This ability initializes the memory's output to a user-defined value.

Intel® FPGA memory also supports asynchronous clear and synchronous clear on output latches and output registers. If the RAM does not use output registers, clear the RAM outputs using the output latch asynchronous clear (aclr). The aclr signal is generated at any time. The internal logic extends the clear pulse until the next rising edge of the output clock. When the aclr signal asserts, the outputs are cleared and stay clear until the next read cycle.