AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Feature Comparison

The following table compares MMCM features in UltraScale+* with PLL features in Intel® Stratix® 10 devices.

Table 52.  MMCM in UltraScale+* versus PLL in Intel® Stratix® 10 Devices
Features AMD* Xilinx* MMCM

( UltraScale+* )


( Intel® Stratix® 10)

Frequency Synthesis Clock Multiplication and Division Yes Yes
Phase Shifting Yes Yes
Clock Duty Cycle Yes Yes
MMCM Deskew Adjust Internal Feedback Yes  
Spread Spectrum Yes Yes
System Synchronous

Normal Mode

Yes Yes
Source Synchronous Yes Yes
Zero Delay Buffer Yes Yes
No Compensation Yes (CMT to CMT connection) Yes (Direct compensation)21
External Feedback Yes Yes
Others Input Clock Switchover Yes Yes
Dynamic re-configuration Yes Yes
Single or Differential Clock Inputs Yes Yes
21 LVDS compensation mode can also be considered as a special case of Source Synchronous Compensation Mode for pins of internal serializer/deserializer (SERDES) capture register.