AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3.7.2. Interface Planner

The Vivado* software supports I/O exploration and assignment via the I/O Planning View Layout.

In the Intel® Quartus® Prime Pro Edition software, the Interface Planner tool (Tools > Interface Planner ) simplifies the planning of accurate constraints for physical implementation after synthesis, with features such as:
  • Prototype interface implementations
  • Plan clocks
  • Rapidly define a legal device floorplan
Figure 8.  Interface Planner GUI