AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.2. FPGA Design Flow Using Command Line Scripting

Automating the FPGA design process saves time and increases productivity. The Vivado* software and the Intel® Quartus® Prime Pro Edition software provide the tools necessary to automate your FPGA design flow.

The compilation flow is the sequence and methods by which the software translates design files, maps the translated design to device-specific elements, places and routes the design in the device, and generates programming files. The Intel® Quartus® Prime Pro Edition software performs these functions through stages such as Analysis and Synthesis, Fitter, Assembler, and Timing Analyzer. If you are familiar with the command-line flow in the Vivado* software, you can detect parallels with the Intel® Quartus® Prime Pro Edition software.

The following figure shows the typical stages of the compilation flow and the corresponding AMD* Xilinx* Vivado* and Intel® FPGA Intel® Quartus® Prime Pro Edition command line instructions for each stage.

Figure 1. Basic Design Flow Stages and Command Line Instructions

The Hyper-Aware Design Flow

The Hyper-Aware Design Flow allows you to take full advantage of the Intel® Hyperflex™ architecture provided on Intel Agilex® 7 and Intel® Stratix® 10 devices. This flow combines automated register retiming (Hyper-Retiming), with implementation of target timing closure recommendations (Fast Forward compilation), to maximize use of Hyper-Registers and drive the highest performance for your Intel Agilex® 7 and Intel® Stratix® 10 designs:

  • Hyper-Retiming:

    A key innovation of the Intel® Hyperflex™ architecture is the addition of multiple Hyper- Registers in every routing segment and block input. Maximizing the use of Hyper-Registers improves design performance. The prevalence of Hyper-Registers improves balance of time delays between registers and mitigates critical path delays.

  • Fast Forward Compilation:

    If you require optimization beyond Hyper-Retiming, run Fast Forward compilation to generate timing closure recommendations that break key performance bottlenecks. Fast Forward compilation shows precisely where to make the most impact with RTL changes, and reports the performance benefits you can expect from each change.