AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

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Document Table of Contents Fractal Synthesis

Fractal Synthesis optimizations can be used for deep-learning accelerators and other high-throughput, arithmetic-intensive designs that exceed all available DSP resources. For such designs, fractal synthesis optimization can achieve 20-45% area reduction.

Fractal synthesis uses techniques such as multiplier regularization and retiming which are ideal for operations like calculating dot-products, and continuous arithmetic packing to pack adder trees, multipliers into logic blocks optimally sized to fit Intel FPGA LABs.