AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

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3.3.17. Partial Reconfiguration

Partial Reconfiguration (PR) allows for the dynamic reprogramming of a portion of the FPGA while the rest of the design continues to function.

With Partial Reconfiguration, you can dynamically reprogramming part of the FPGA device while the rest of the design continues to function.

You can define multiple personas for a particular region in the design, without impacting operation in areas outside this region. This methodology is effective in systems where multiple functions time-share the same FPGA device resources. PR configuration can be performed either with an internal host or through an external host using dedicated PR pins on the device. It provides the following advancements to a flat design:

  • Allows run-time design reconfiguration
  • Increases scalability of the design
  • Reduces system down-time
  • Supports dynamic time-multiplexing functions in the design
  • Lowers cost and power consumption through efficient use of board space