AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

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Document Table of Contents Port Mapping Reference

The following table shows the mapping between MMCM UltraScale* ports, created with the AMD* Xilinx* IP Catalog, and PLL ports in Intel® Stratix® 10 device, created with the IP Catalog.

Table 53.  Port-Mapping MMCM UltraScale* versus PLL Intel® Stratix® 10
AMD* Xilinx* MMCM Core Port Intel® FPGA Intel® FPGA IOPLL IP Core Port Description
clk_in1 refclk First clock input
clk_in2 refclk1 Second clock input
clkfb_in fbclk External clock feedback
clkfbout fboutclk Feeds into the feedback port
activeclk Output signal that indicates which reference clock source the I/O PLL uses
clk_in_sel extswitch Switch between input clock ports
reset rst Asynchronous reset port
clk_out1, clk_out2, clk_outX outclk_[] Clock frequency output ports.

AMD* Xilinx* MMCM has fixed settings for most outputs, and you can configure the Intel® FPGA IOPLL IP core to suit them.

clkinstopped clkbad[1..0] Indicates whether the clock input signal stopped switching
clkfb_stopped Specifies whether the feedback clock stopped
locked locked Specifies whether the PLL is locked
adjpllin Input signal that feeds from upstream I/O PLL
cascade_out Output signal that feeds into downstream I/O PLL

Bidirectional port that connects to the mimic circuitry. You connect this port to a bidirectional pin that is placed on the positive feedback dedicated output pin of the I/O PLL.

The zdbfbclk port is available only if the I/O PLL is in zero-delay buffer mode.

AMD* Xilinx* MMCM Core Port Dynamic Phase Shift Ports in Intel® FPGA IOPLL Description
psclk scanclk Specifies clock that drives the dynamic phase shift operation
psen phase_en Start dynamic phase-shift operation
psincdec updn Specifies direction of phase shift operation
cntsel Specifies counter for dynamic phase shift operation
num_phase_shift Specifies number of phase shifts per dynamic phase shift operation
psdone phase_done Specifies completion of dynamic phase shift operation
power_down Enables power_down input port for user selection

For more information about using dynamic PLL reconfiguration, refer to the Phase-Locked Loops ( Intel® FPGA IOPLL) IP Core User Guide.