AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

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4.3. Setting Equivalent AMD* Xilinx* Design Constraints

AMD* Xilinx* designs store all the constraints and attributes in AMD* Xilinx* Design Constraint (.xdc) files, including timing and device constraints. Intel® FPGA designs use separate files for device (.qsf) and timing (.sdc) constraints. The Design Constraints section in FPGA Tools Comparison lists the appropriate GUIs to enter design constraints.

Note: AMD* Xilinx* -based placement constraints do not carry over to Intel® FPGA placement constraints. Avoid making placement constraints to a design until you finish the conversion to the Intel® Quartus® Prime software.