AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

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Document Table of Contents IOSTANDARD

Equivalent to the IOSTANDARD constraint in AMD* Xilinx* , the IO_STANDARD logic option uniquely defines the input and output (VCCIO) voltage, reference VREF voltage (if applicable), and the types of input and output buffers used for I/O pins.

The following example shows how to set the equivalent IOSTANDARD constraint (Differential SSTL-2 Class I) to the “q2” output.

Example XDC command:

# Set Differential SSTL18_I I/O Standard to q2
set_property IOSTANDARD SSTL18_I [get_ports q2];

Equivalent QSF command:

# Set Differential SSTL-18 Class I I/O Standard to q2
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to q2