AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023

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4.4. Setting Up the Simulation Environment

Intel® Quartus® Prime Pro Edition software supports RTL and gate-level design simulation in the EDA simulators listed in the table. Unless you use a simulator specific to AMD* Xilinx* , the simulation environment in the Intel® Quartus® Prime Pro Edition is similar. The AMD* Xilinx* environment also supports all the following EDA simulators:

Table 63.  Supported Simulators
Simulation Tools Version
Aldec* Active-HDL* 13.0 (Windows* only)
Aldec* Riviera-PRO* 2023.04
Cadence* Xcelium* Parallel Logic Simulation 22.09.001 (Linux* only)
Questa*-Intel® FPGA Edition 2023.1
Siemens* EDA ModelSim SE 2022.4
Siemens* EDA Questa* Advanced Simulator 2022.4
Synopsys* VCS* and VCS* MX T-2022.06-SP2-3 (Linux* only)

For more information about Questa* Intel® FPGA Edition software refer to the Questa-Intel FPGA Edition Software page of the Intel FPGA website.