AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 4/01/2024
Public
Document Table of Contents

4.2.3.3. Example: Converting to the LPM_MULT IP Core

You can convert the AMD* Xilinx* Multiplier Core that targets a AMD* Xilinx* device into multipliers for an Intel® FPGA device by using the IP Catalog.
In this example, the test module instantiates the mymult module, created using the AMD* Xilinx* Core Generator. The parameters are:
Table 58.  Parameters of Multiplier Module
Parameter Value
Multiplier Type Parallel multiplier where neither of the input buses is a constant value
Input data width 18 bits
Input data type Signed
Output result width Restricted to 36 bits
Number of pipeline stages 2
Implemented using Multipliers and optimized for Speed
The Original Verilog HDL Code in the Vivado* Software is:
module top(
        input clk,
        input [17:0] a,
        input [17:0] b,
        input ce,
        input sclr,
        output [35:0] p
        );
mymult i1 (
    .CLK(clk),
    .A(a), // Bus [17: 0]
    .B(b), // Bus [17: 0]
    .CE(ce),
    .SCLR(sclr),
    .P(p)); // Bus [35: 0]
endmodule
The original VHDL Code in the Vivado* Software is:
LIBRARY ieee;
USE ieee.std_logic_1164.all; LIBRARY work;

ENTITY test IS
port (
        clk: IN STD_LOGIC;
        a: IN STD_LOGIC_VECTOR(17 downto 0);
        b: IN STD_LOGIC_VECTOR(17 downto 0);
        sclr: IN STD_LOGIC;
        ce: IN STD_LOGIC;
        p: OUT STD_LOGIC_VECTOR(35 downto 0)
        );
END test;

ARCHITECTURE arch OF test IS 

component mymult
        PORT(
            CLK: IN STD_LOGIC;
            A: IN STD_LOGIC_VECTOR(17 downto 0);
            B: IN STD_LOGIC_VECTOR(17 downto 0);
            CE: IN STD_LOGIC;
            SCLR: IN STD_LOGIC;
            P: OUT STD_LOGIC_VECTOR(35 downto 0)
            );
end component;

BEGIN
i1: mymult
PORT MAP(CLK => clk,
A => a, B => b, CE => ce,
SCLR => sclr, P => p);
END;
In the IP Catalog, select the LPM_MULT IP core to create the equivalent mymult module.
Converted Verilog HDL Code in the Quartus® Prime Pro Edition software:
module test(
            input clk,
            input [17:0] a,
            input [17:0] b,
            input ce,
            input sclr,
            output [35:0] p
            );
mymult i1 (
        .clock(clk),
        .dataa(a), // Bus [17: 0]
        .datab(b), // Bus [17: 0]
        .clken(ce),
        .sclr(sclr),
        .result(p)); // Bus [35: 0]
endmodule
Converted VHDL Code in the Quartus® Prime Pro Edition Software
LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY test IS
        port (
            clk: IN STD_LOGIC;   
            a: IN STD_LOGIC_VECTOR(17 downto 0);
            b: IN STD_LOGIC_VECTOR(17 downto 0);
            ce: IN STD_LOGIC;
            sclr: IN STD_LOGIC;
            p: OUT STD_LOGIC_VECTOR(35 downto 0)
            );
END test;

ARCHITECTURE arch OF test IS

component mymult
    PORT(clock: IN STD_LOGIC;
        dataa: IN STD_LOGIC_VECTOR(17 downto 0);
        datab: IN STD_LOGIC_VECTOR(17 downto 0);
        clken: IN STD_LOGIC;
        sclr: IN STD_LOGIC;
        result: OUT STD_LOGIC_VECTOR(35 downto 0)
    );
end component;

BEGIN
i1: mymult
PORT MAP(clock => clk,
        dataa => a,
        datab => b,
        clken => ce,
        sclr => sclr,
        result => p);
END;