AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 4/01/2024
Public
Document Table of Contents

4.1. Replacing AMD* Xilinx* Primitives

When migrating a design, you must convert common AMD* Xilinx* primitives to the Intel® FPGA equivalents. Primitives are the basic building blocks of a AMD* Xilinx* design. Primitives perform dedicated functions in the device, and implement standards for I/O pins in AMD* Xilinx* devices. Primitives names are standard.

The following table lists common AMD* Xilinx* primitives and describes the equivalent Intel® FPGA design element.

Table 40.  Common AMD* Xilinx* Device-Specific Primitives and Intel® FPGA Equivalents
AMD* Xilinx* Primitive Description Intel® FPGA Equivalent Conversion Method
IBUF Single Input Buffer wire/signal Assignment HDL
OBUF Single Output Buffer wire/signal Assignment
BUFG Global Clock Buffer wire/signal and Global Signal Assignment HDL and Assignment Editor
IBUFG_<selectable I/O standard> 13 Input Global Buffer with selectable interface wire/signal, I/O Standard, and Global Signal Assignment 14
IBUF_<selectable I/O standard> 13 Input buffer with selectable interface wire/signal and I/O Standard Assignment14
IOBUF_<selectable I/O standard> 13 Bidirectional buffer with selectable interface wire/signal and I/O Standard Assignment14
OBUFG_<selectable I/O standard> 13 Output Global Buffer with selectable interface wire/signal and I/O Standard Assignment14
OBUF_<selectable I/O standard> 13 Output buffer with selectable interface wire/signal and I/O Standard Assignment14
IBUFDS, OBUFDS Differential I/O Buffer wire/signal and I/O Standard Assignment14
SRL16 16-bit Shift Register AUTO_SHIFT_REGISTER_RECOGNITION Assignment Editor
13 The attributes of the <selectable I/O standard> are device-specific. For specific I/O standard information, refer to the AMD* Xilinx* device’s data sheet.
14 For differential I/O buffer, you can assign differential I/O standard to the desired differential I/O signal. The Quartus® Prime software automatically creates a new signal, signal_name(n), that is opposite in phase with the desired signal.