AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 4/01/2024
Public
Document Table of Contents

3.3.13.2. Signal Tap Logic Analyzer

The Vivado® software includes the Integrated Logic Analyzer (ILA) feature to debug post-implemented designs on a FPGA. Similarly, the Quartus® Prime provides the Signal Tap logic analyzer; a multiple-input, digital acquisition instrument that captures and stores signal activity from any internal device node or nodes. The Signal Tap logic analyzer helps debug an FPGA design by probing the state of the internal signals in the design without using external equipment.
Table 28.   Signal Tap Logic Analyzer Features and Usage
Features Typical Usage
  • Uses FPGA resources.
  • Captures data continuously from the signals you specify while the logic analyzer is running. To capture and store only specific signal data, you specify conditions that trigger the start or stop of data capture. A trigger activates when the trigger conditions are met, stopping analysis and displaying the data
You have spare on-chip memory and you want functional verification of a design running in hardware.