AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 4/01/2024
Public
Document Table of Contents

3.3.8. Viewing and Editing Design Placement

The Vivado* software provides the Device Window for floorplanning and design analysis. In the Quartus® Prime Pro Edition software, the Chip Planner simplifies floorplan analysis by providing visual display of chip resources.
Table 19.  Design Placement Methods Comparison
GUI Feature AMD* Xilinx* Vivado* Software Quartus® Prime Pro Edition Software
Viewing and Editing Design Placement

Device Window (in I/O Planner View Layout)

Package Window (in I/O Planner View Layout)

Chip Planner

With the Chip Planner, you can view post-compilation placement, connections, and routing paths. You can also make assignment changes, such as creating and deleting resource assignments.

Figure 9. Chip Planner

To open the Chip Planner, click Tools > Chip Planner.