AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 4/01/2024
Public
Document Table of Contents

3.3.5. Synthesis

The Quartus® Prime Pro Edition Synthesis provides full support for VHDL, Verilog HDL, SystemVerilog, and Block Design File (.bdf) schematic entry.
Table 16.  Synthesis Comparison
GUI Feature AMD* Xilinx* Vivado* Software Quartus® Prime Pro Edition Software
Synthesis Synthesis Analysis and Synthesis
Third-Party EDA Synthesis Third-Party EDA Synthesis

Features

The Quartus® Prime Pro Edition Synthesis engine enforces strict industry-standard HDL structures.

Synthesis supports Verilog Quartus Mapping (.vqm) files generated by third-party EDA tools. It can also generate a .vqm netlist with quartus_eda that can be used with other EDA tools.

At the end of synthesis, the Compiler generates an atom netlist, which is a database of the atom elements that design synthesis requires to implement the design in silicon. The Analysis & Synthesis module of the Compiler creates one or more project databases for each design partition. You can specify various settings that affect synthesis processing.

Access

The Assignments > Settings > IP Settings dialog box allows you to control the IP regeneration stage for synthesis or simulation

The Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis) dialog box allows you to set options that affect the analysis and synthesis stage of the compilation flow. These options include Optimization Technique, State Machine Processing, Restructure Multiplexers, and others.