AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 4/01/2024
Public
Document Table of Contents

7. Document Revision History for Intel® FPGA Design Flow for AMD* Xilinx* Users

Document Version Quartus® Prime Version Changes
2023.04.01 24.1
  • Added information for Agilex™ 5 devices
2023.09.08 23.2
  • Added information about DSP register packing restrictions to "Design Implementation".
  • Renamed "Xilinx" to "AMD Xilinx" where needed.
2022.02.25 21.3
  • Revised content for Quartus® Prime Pro Edition software version 21.3 and Xilinx* Vivado* Design Suite version 2020.2.
  • Updated the ECC Parity Flip ( Stratix® 10 Devices only) topic to correct the parity bit sequence for double-adjacent-error correction.
  • Removed the set_clock_groups section. The include_generated_clocks switch of the set_clock_groups constraint has been supported by Quartus® Prime Pro Edition since Version 19.3.
2020.08.24 17.1.0
2018.03.20 17.1.0
  • Revised content for Quartus® Prime Pro Edition software version 17.1 and Xilinx* Vivado* Design Suite version 2017.2.
  • Added chapter that compares latest devices.
  • Updated for latest Intel® naming conventions.
May 2015 2015.05.11
  • Updated content for DSE II
  • Updated GUI screenshots to v15.0
  • Removed obsolete devices not supported in v15.0
  • Removed MegaWizard Plug-in Manager content and replaced with IP Catalog/Parameter Editor content
  • Updated links
March 2013 7.0
  • Revised content for software versions ISE 14.2 and Quartus II 12.1
  • Removed outdated design examples.
  • Updated template
November 2009 6.2 Corrected set_max_delay constraint equivalents for OFFSET IN BEFORE and OFFSET OUTPUT AFTER UCF commands in Timing Constraints section.
April 2009 6.2 Added Appendix A: Design Example and Appendix B
July 2008 6.0 Revised and restructured content for software versions ISE 10.1 and Quartus II 8.0
June 2005 5.0
  • Revised content for software versions ISE 7.1 and Quartus II 5.0
  • Updated terminology
  • Added Pin Planner subsection
  • Added Quartus II Incremental Compilation
February 2004 4.0
  • Revised content for software versions ISE 6.3i and Quartus II 4.2
  • Updated Table 6 for Power
  • Updated cross-probing chart
January 2004 3.1 Updated terminology
October 2003 3.0
  • Revised content for software versions ISE 6.2i and Quartus II 4.1 sp2
  • Added information on cross-probing
July 2003 2.0
  • Revised content for software versions ISE 5.1i and Quartus II 3.0
  • Added information on the Quartus II modular executables and command-line scripting
  • Added information on DDR RAM conversions
November 2002 1.0 Initial release.