AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 4/01/2024
Public
Document Table of Contents

4.2.3.4. Example: Converting to the Intel® FPGA Multiply Adder IP core

The following example shows VHDL multipliers compiled in the Quartus® Prime Pro Edition Software after the conversion. The IP Catalog implements the Multiply Adder IP core by creating the mymult_add module.

The converted VHDL Code in the Quartus® Prime Pro Edition Software is:
LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY test IS
        port
        (
        clk:IN STD_LOGIC;
        a: IN STD_LOGIC_VECTOR(17 downto 0);
        b: IN STD_LOGIC_VECTOR(17 downto 0);
        ce: IN STD_LOGIC;
        sclr: IN STD_LOGIC;
        p: OUT STD_LOGIC_VECTOR(35 downto 0)
        );
END test;

ARCHITECTURE arch OF test IS

component mymult_add
    PORT(
        clock0: IN STD_LOGIC;
        dataa_0: IN STD_LOGIC_VECTOR(17 downto 0);
        datab_0: IN STD_LOGIC_VECTOR(17 downto 0);
        ena0: IN STD_LOGIC;
        sclr0: IN STD_LOGIC;
        result: OUT STD_LOGIC_VECTOR(35 downto 0)
    );
end component;
BEGIN
i1: mymult_add
PORT MAP(clock0 => clk,
        dataa_0 => a,
        datab_0 => b,
        ena0 => ce,
        sclr0 => sclr,
        result => p);
END;