AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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Document Table of Contents Write and Read Operation Triggering

Ensure to resolve potential write contentions external to the RAM, because writing to the same address location at both ports results in unknown data storage at that location. Therefore, knowing when the write operation was triggered is crucial.

For Intel® Arria® 10 devices, the write operation in Intel® FPGA memory can occur at either falling clock edges or rising clock edges, depending on the type of embedded memory block. For Intel® Agilex™ and Intel® Stratix® 10 devices, the write operation is triggered at rising clock edges.

To avoid delta delay, do not trigger control signals together with clock signals.