AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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Document Table of Contents Port Mapping

The following table shows the port mapping between the Xilinx* Multiplier Core and the Intel® FPGA LPM_MULT IP core.

Table 57.  Port Mapping Between Xilinx* Multiplier Core and LPM_MULT IP Core
Xilinx* Multiplier Core Port Intel® FPGA LPM_MULT IP Core Port Description
A [] dataa [] Data Input Port A
B [] datab [] Data Input Port B
CLK [] clock Clock Port
CE clken Clock Enable Port
SCLR sclr Synchronous Clear Port
N/A aclr Asynchronous Clear Port
P [] result [] Multiplication Result Port