AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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3.3.14. View Netlist

Similar to the Netlist Window and Schematic Window features available in the Vivado* software to generate logical or physical hierarchy, the Intel® Quartus® Prime Pro Edition RTL Viewer and Technology Map Viewer provide powerful ways to view initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.

Table 36.  View Netlist Methods Comparison
GUI Feature Xilinx* Vivado* Software Intel® Quartus® Prime Pro Edition Software
View Netlist

Schematic Window (Elaborated)

Schematic Window (Synthesized)

Schematic Window (Implemented)

RTL Viewer (Post Synthesis)

Technology Map Viewer (Post-Mapping)

Technology Map Viewer (Post-Fitting)

Fast Forward Viewer (Post-Fitting)

The Technology Map Viewer can display netlists at different fitter snapshots of the design by using Snapshot Viewer.