AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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Document Table of Contents IOB

Equivalent to the IOB constraint in Xilinx* , the FAST_INPUT_REGISTER and FAST_OUTPUT_REGISTER logic options directs the Compiler to implement an input register and output register in an I/O cell that has a fast, direct connection from an I/O pin.

The following example shows how to set the equivalent IOB constraint to the input “d1” or the output “q1”.

Example of XDC command:

# Set IOB to input d1
set_property IOB TRUE [get_ports d1];

# Set IOB to output q1
set_property IOB TRUE [get_ports q1];

Equivalent QSF command:

# Set FAST_INPUT_REGSITER to input d1
set_instance_assignment -name FAST_INPUT_REGISTER ON -to d1

# Set FAST_OUTPUT_REGSITER to output q1
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to q1

For more information about the slew fast input and output register features in the device, refer to the specific device handbook and the Intel® Quartus® Prime Help.