AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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Document Table of Contents Fast Preservation

In Xilinx Vivado designs, the Incremental Compile design flow speeds up place and route runtime.

In Intel® Quartus® Prime Pro Edition, enabling the Fast Preserve option on the Incremental Compile tab under Assignment > Settings > Compiler Settings specifies that the Compiler can simplify a final snapshot of a partition to only its interface logic.

To use Fast Preservation effectively, ensure that your designs are floorplanned and partitioned and have a well-separated periphery.