AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3.2.2. PACKAGE_PIN

Equivalent to the PACKAGE_PIN constraint in the Xilinx* Vivado* software, PIN_<pin number> is the pin location constraint assignment that the Intel® Quartus® Prime Pro Edition uses.

The following example shows how to set the location for a clock pin on the device.

Example of XDC Command:

# Assign location for the clock pin
set_property PACKAGE_PIN B26 [get_ports clock]

Equivalent QSF Command:

# Assign location for the clock pin
set_location_assignment PIN_AU33 -to clock