AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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Document Table of Contents Byte Enable

To ensure that the operation writes only specific bytes of data, embedded memory blocks support the byte enable property, that masks the input data. The unwritten bytes or bits retain the previous value.
Note: Xilinx* RAMs support byte enable in Virtex* -4 and newer devices.

The following table compares byte enable implementation in Xilinx* and Intel® FPGA RAMs

Table 47.  Byte Enables Differences in Xilinx* RAM and Intel® FPGA RAM
Differences Xilinx* RAM Intel® FPGA RAM
Controlling signals

The WEA[n:0] signal controls the byte enable.

Each bit in WEA[n:0] acts as a write enable for the corresponding input data byte.

Uses two signals, write enable (wren) and byte enable (byteena).

To control which byte to write, assert the wren signal and the specific bit of the byteena signal. For example, in a RAM block in x16 mode:
byte_enable Writing on data[7..0] Writing on data[15..8]
01 Enabled Disabled
11 Enabled Enabled
To create a byteena port, the width of the input data port must be a multiple of the byte size for the port.
Input data width support Support multiples of 8 or 9 bits. Support multiples of 5, 8, 9, 10 bits. For configurations smaller than two bytes wide, the write_enable or clock_enable signals control the write operation.17
Output value of masked byte when performing read-during-write to the same location. Output depends on read-during-write configuration:
Output depends on the type of memory block:
Memory Block Output of Masked Bytes
True dual Port DONT_CARE
Simple Quad port DONT_CARE
17 Only MLAB memory blocks support byte_enable for input data width that is multiple of 5.