AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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3.3.4. Design Constraints

The Vivado* software provides GUI editors (Device/Physical/Timing windows) to create and edit design constraints. Xilinx* designs store all the constraints and attributes in Xilinx* Design Constraint (.xdc) files, including timing and device constraints. You can also edit .xdc files with a text editor.

Intel® FPGA designs use separate files for device (.qsf) and timing (.sdc) constraints, and stores timing constraints in Synopsys* Design Constraints (SDC) format. To view and edit pin assignments, device options, and logic options, use the Assignment Editor. To view and edit timing constraints, use the Text Editor in the Timing Analyzer GUI.

Table 14.  Design Constraint Comparison
GUI Feature Xilinx* Vivado* Software Intel® Quartus® Prime Pro Edition Software
Design Constraints Device, Physical and Timing Constraints window

Assignment Editor,

Timing Analyzer Text Editor


The table summarizes the file format and assignment types that the tools in the Intel® Quartus® Prime Pro Edition software set.

Table 15.   Intel® Quartus® Prime Pro Edition Assignment Tools
Assignment Type File Format Tools to Make Assignments
Timing SDC Timing Analyzer
I/O-related TCL Timing Analyzer
QSF Pin Planner, Interface Planner
Others Assignment Editor

With separate constraint files, you avoid searching for timing constraints among other device constraints. Additionally, you can modify the timing constraints and check for validity without recompiling. In place of the I/O Planning in the Vivado* software, Intel® Quartus® Prime Pro Edition software offers the Interface Planner to plan interfaces and device periphery, and the Pin Planner to edit, validate, and export pin assignments.

For equivalence between design constraints, refer to the Set Equivalent Xilinx* Design Constraints section.