AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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Document Table of Contents

3.3.2. Design Entry

The Intel® Quartus® Prime software supports all the design entry methods that the Vivado* software supports.
Table 12.  Design Entry Methods Comparison
GUI Feature Xilinx* Vivado* Software Intel® Quartus® Prime Pro Edition Software
Design Entry HDL Editor HDL Editor
EDA Netlist EDA Netlist
- Schematic/Block Editor
- State Machine Editor
- State Machine Viewer
IP Catalog IP Catalog and Parameter Editor
IP Integrator Platform Designer System Integration Tool
IP Packager Platform Designer Component Editor

Managing Project Files

In the Xilinx* Vivado* software, you use the Add Source dialog box to add or remove existing design files. To add or remove existing design files from a project in the Intel® Quartus® Prime software:

  • Click Assignments > Settings to open the Settings dialog box.
  • In the Category list, select Files to open the Files page. This page allows you to add or remove files.