AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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Document Table of Contents Clocking Mode

In Intel® FPGAs, the clock mode depend on which embedded memory block you select:

Table 43.  Clocking Mode
Intel® FPGA Clocking Mode Description Comment
Single All ports share the common clock.  
Input/output A separate clock is available for input ports and output ports.

Xilinx* memories do not differentiate these two clocking modes. However, the clocking mode behavior with simple dual-port RAM can be identical to Intel® FPGA clocking mode in the following situations:

Port A Port B Identical to
Input Output Input/output clock mode
Write Read Read/write clock mode
Read/write A separate clock is available for read ports and write ports.

For more information about supported clocking modes, refer to the Intel® Stratix® 10 Embedded Memory User Guide.