AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022
Public

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4.3.2.3. LOC & BEL

In the Xilinx* Vivado* software, the LOC constraint specifies the placement of a logic cell to a specific SLICE, and the BEL constraint specifies the placement of a leaf cell within the SLICE. The Xilinx* Vivado* software uses the LOC & BEL constraints to place a register or LUT or SRL or memory to a specific location. An equivalent constraint in the Intel® Quartus® Prime Pro Edition software is <Location> -to <value>.

The following example shows how to constraint the location for a current node on the device.

Example of XDC Command:

# Assign location for an internal register
set_property LOC SLICE_X0Y0 [get_cells uut_inst/dout_reg]

Equivalent QSF Command:

# Assign location for an internal register
set_location_assignment FF_X60_Y119_N55 -to uut_inst|dout_reg