AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022
Public

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3.3.12.1. Simulation Models for Designs Containing LPMs or IP Cores

Functional Simulation

The Intel® Quartus® Prime Pro Edition software provides functional simulation models that allow you to perform functional/behavioral simulation on designs containing LPMs or Intel® FPGA IP cores.

Table 24.  Simulation Model Files
  Verilog HDL VHDL
LPM 220model.v

220pack.vhd

220model.vhd

Intel® FPGA IP cores altera_mf.v

altera_mf.vhd

altera_mf_components.vhd

Gate-level Functional Simulation

To perform gate-level functional simulation on a design, the Intel® Quartus® Prime Pro Edition software generates output netlist files containing information about how the design was placed into device-specific architectural blocks.

Table 25.  Generated Output Files
  Extension
Verilog HDL output file .vo
VHDL output file .vho

You can perform simulations with pre-compiled model libraries by using the Questa* Intel® FPGA Starter Edition simulator included in the Intel® Quartus® Prime Pro Edition software. You can also compile your own selection of model libraries with the Simulation Library Compiler tool in the Intel® Quartus® Prime Pro Edition software.