AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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Document Table of Contents Memory Port Mapping

The following table lists the memory ports that the Vivado* ’s IP Catalog generates, and their corresponding mapping to Intel® FPGA memory ports for different memory modes.

Table 49.  Block Memory Generator's Memory Port Mapping to Intel® FPGA Memory Ports
Port Description Xilinx* Ports Port-Mapping to Intel® FPGA Ports in Different Memory Modes
Single-Port RAM Simple Dual-Port RAM True Dual-Port RAM Single-Port ROM Dual-Port ROM
Port A: address addra address wraddress wraddress/ address_a address address_a
Port A: data input dina data data data/ data_a
Port A: parity data input dinpa
Port A: clock enable for the input register ena inclocken/ clken inclocken/ wrclocken/ enable inclocken/ wrclocken/ enable inclocken/ clken enable
Port A: clock enable for the last output register regcea, ena outclocken/ clken enable outclocken/ enable outclocken/clken enable
Port A: write enable NA wren wren wren/ wren_a NA NA
Port A: byte enable18 wea byteena byteena_a byteena_a NA NA
Port A: asynchronous clear NA outaclr/ aclr NA out_aclr/ rd_aclr/ aclr outaclr/aclr aclr
Port A: synchronous set/reset rsta/ rstrega sclr NA sclr sclr sclr
Port A: read enable ena (in SDP 19 mode) rden NA rden_a/ rden rden rden_a
Port A: in clock clka inclock/ clock inclock/ wrclock/ clock inclock/ wrclock/ clock inclock/ clock clock
Port A: out clock NA outclock/ clock NA NA outclock/ clock NA
Port A: data output douta q NA q/ q_a q q_a
Port A: parity data output doutpa
Port A: address enable addrena 20 addressstall_a wr_addressstall wr_addressstall/ addressstall_a addressstall_a addressstall_a
Port B: address addrb NA rdaddress rdaddress/ address_b NA address_b
Port B: data input dinb NA NA data_b NA NA
Port B: parity data input dinpb
Port B: clock enable for the input register enb NA NA inclocken/enable NA enable
Port B: clock enable for the last output register regceb, enb NA outclocken/ rdoutclocken outclocken/enable NA enable
Port B: write enable enb (in SDP19 mode) NA NA wren_b NA NA
Port B: byte enable web NA NA byteena_b NA NA
Port B: asynchronous clear NA out_aclr/ rd_aclr/ aclr rd_aclr/ out_aclr NA aclr
Port B: synchronous set/reset rstb/ rstregb NA sclr sclr NA sclr
Port B: read enable NA rden rden_b NA rden_b
Port B: clock clkb outclock/ clock outclock/ rdclock/ clock outclock/ rdclock outclock/ clock clock
Port B: data output doutb NA q q/ q_b NA q_b
Port B: address enable addrenb NA rd_addressstall rd_addressstall/ addressstall_b NA addressstall_b
Port B: parity data output doutpb
Single bit error sbiterr NA eccstatus[1:0] NA NA NA
Double bit error dbiterr NA NA NA NA
ECC encoder bypass port NA eccencbypass NA NA NA
ECC parity flip port NA eccncparity[7:0] NA NA NA
Inject single bit error injectsberr NA
Inject double bit error injectdbiterr NA

You can also infer RAM in HDL. For more information, refer to the Recommended HDL Coding Styles in Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations.

18 For configurations less that two bytes wide, Xilinx* write enable signals (wea and web) are equivalent to Intel® FPGA write enable signals (wren, wren_a, or wren_b) signals, depending on the memory mode used. For configurations of more than two bytes, Xilinx* 's write enable buses (wea[] and web[]) are equivalent to Intel® FPGA byte enable buses(byteena[], byteena_a[], or byteena_b[]), depending on the memory mode used. Also, the Intel® FPGA write enable signal needs to be asserted for the write operation.
19 Xilinx* simple dual-port RAM generated through Block Memory Generator
20 Port mappings denoted with NA are not applicable for that memory mode; port-mappings denoted with — are not supported in Intel® FPGA memory.