AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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4.4.1. Simulation Levels

The Intel® Quartus® Prime Pro Edition software supports RTL and gate-level simulation in the supported EDA Simulators.

If you use the Questa* Intel® FPGA Edition Simulator in a design that includes deep levels of hierarchy, turn off the Maintain hierarchy EDA tools option. This action prevents the Compiler to generate a large number of module instances in post-fit or post-map netlist, thus exceeding the Questa* Intel® FPGA Edition instance limitation. To access this option, click Assignments > Settings > EDA Tool Settings > More Settings.

For information about Questa* Intel® FPGA Edition Products, refer to the Questa* Intel® FPGA Edition page of the Intel FPGA website.

For information about supported simulation levels, refer to Intel Quartus Prime Pro Edition User Guide: Third-party Simulation.