AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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Document Table of Contents report_timing

In place of the report_timing_summary executable that the Vivado* software provides for performing a static timing analysis on your design, the Intel® Quartus® Prime Pro Edition software provides the quartus_sta executable.

To specify timing constrains, the Intel® Quartus® Prime Pro Edition software uses the industry standard Synopsys* Design Constraint (SDC) file format. The Xilinx* 's Design Constraint File (.xdc) constraint format is based on the SDC format. For details on converting XDC to SDC files, refer to the Timing Constraints section.

This example performs timing analysis on the filtref project using the SDC timing constraints file, filtref.sdc, to determine whether the design meets the timing requirements:

quartus_sta filtref --sdc=filtref.sdc

For command line help, type quartus_sta --help at the command prompt.