AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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3.3.9. Static Timing Analysis

The Report Timing Summary in Vivado* generates the Post-Place and Post-Route Static Timing Report. Similarly, the Intel® FPGA Timing Analyzer analyzes and reports the performance of all logic in your design, allowing you to determine all the critical paths that limit your design’s performance.
Table 20.  Static Timing Analysis Methods Comparison
GUI Feature Xilinx* Vivado* Software Intel® Quartus® Prime Pro Edition Software
Static Timing Analysis Report Timing Timing Analyzer

The Intel® FPGA Timing Analyzer is an easy-to-use, second-generation, ASIC-strength static timing analyzer that supports the industry-standard Synopsys* Design Constraints (SDC) format.

Figure 10.  Timing Analyzer GUI

The major difference between performing timing analysis with the Report Timing Summary in Vivado* and the Intel® FPGA Timing Analyzer is that in the Vivado* software, a change in timing constraint triggers a recompile. In contrast, the Timing Analyzer GUI allows you to experiment with timing constraints and timing model without recompiling.


Static timing analysis with the Timing Analyzer is part of the full compilation flow, but you can also run the module separately.

To run the Timing Analyzer over a post-fit netlist, click Processing > Start > Start Timing Analyzer .

To open the Timing Analyzer GUI, click Tools > Timing Analyzer .