AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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Document Table of Contents Example: Converting Xilinx* MMCM into an Intel® PLL

This example uses a mymmcm module generated with the Xilinx* IP Catalog. The top module instantiates the mymmccm module with i1. The parameters are:

Table 54.  Example Parameters
Parameter Value
Input Clock Frequency 100 MHz
Clock frequency output port clk_out1 Divide by 2 (50 MHz).
Clock frequency output port clk_out2 Multiply by 4 (400 MHz).
Original Verilog Code in the Vivado* Software:
module top(
            // Clock out ports
            output clk_out1,
            output clk_out2,
            // Status and control signals
            input reset,
            output locked,
            // Clock in ports
            input clk_in1
mymmcm i1 (

To recreate the same behavior using Intel® FPGA software:

  1. In the IP Catalog/Parameter Editor, point to Library > Basic Functions > Clocks, PLLs and Resets > PLL, and double-click Intel® FPGA IOPLL.
    Figure 13.  Intel® FPGA IOPLL on IP Catalog
  2. Generate an IP variant named mypll.
  3. In the Parameter Editor, set the following parameters:
    Table 55.  Parameters of mypll
      Reference Clock Frequency 100 MHz  
    Output Clocks  
      Number of Clocks 2 Specifies the number of clocks that your design requires
      Clock Name clk_out11  
      Desired Frequency 50 MHz  
      Clock Name clk_out2  
      Desired Frequency 400 MHz  
  4. Click Finish.
  5. Create a top module, and instantiate the mypll module with i1.
The converted Verilog HDL code in the Intel® Quartus® Prime Software is:
module top(output clk_out1,
    output clk_out2,
    input reset,
    output locked,
    input clk_in1);
mypll i1(.rst(reset),
        .locked (locked),
        .outclk_0 (clk_out1),
end module