AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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Document Table of Contents Engineering Change Order (ECO) Flow

The Xilinx Vivado Engineering Change Order (ECO) flow allows you to modify a post-implementation design and generate reports and programming files.

Intel® Quartus® Prime Pro Edition has an ECO Compilation Flow that supports last-minute, targeted design changes including changing routing connections; changing IOPLL frequencies by modifying the input reference clock frequency; modifying LUT masks; I/O pin settings such as slew rate, current strength, and delay chain; creating, removing, or placing individual nodes; and inserting wireluts.