AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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4.3.1. Device Constraints

The following table summarizes the most common Xilinx* device constraints and Intel® FPGA equivalent device constraints.

Table 59.   Intel® FPGA Equivalent Device Constraints
Xilinx* Constraint Intel® FPGA Constraint Description
Assignment Name QSF Variable
DRIVE Current Strength CURRENT_STRENGTH_NEW Controls the output pin current value
SLEW Slew Rate SLEW_RATE Turns on Fast Slew Rate Control.
IOB Fast Input Register

Fast Output Register



Specifies whether the Compiler places a register in the device's IOB.
IOSTANDARD IO Standard IO_STANDARD Specifies the I/O standard for an I/O pin
KEEP Implement as Output of Logic Cell "attribute keep" (VHDL)

"synthesis keep" (Verilog)

Prevents a net from either being absorbed by a block or synthesized out.

To set or modify a device constraint, use the Intel® Quartus® Prime Assignment Editor. Alternatively, you can edit the .qsf file.