AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 2/25/2022

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Document Table of Contents Design Assistant

Xilinx Vivado* has a Report Design Rule Checking (DRC) feature that checks design rules on a synthesized or implemented design.

The Design Assistant feature in Quartus similarly performs targeted rule checks and guidance at each stage of compilation, reducing the total number of design iterations.

Design Assistant rule categories include block-based design and partial reconfiguration, clock domain crossings, clocks, floorplanning, linting, platform designer interface, project, reset domain crossing, reset, and timing closure.

Design Assistant identifies rule violations and provides recommendations to help resolve these issues.