AN 307: Intel® FPGA Design Flow for Xilinx* Users

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ID 683562
Date 2/25/2022
Public
Document Table of Contents

1. Introduction to Intel® FPGA Design Flow for Xilinx* Users

Updated for:
Intel® Quartus® Prime Design Suite 21.3
Designing for Intel® FPGA devices is similar in concept and practice to designing for Xilinx* FPGA devices. In most cases, you can import your register transfer level (RTL) into the Intel® Quartus® Prime Pro Edition software and begin compiling your design to the target device.

This document is intended for Xilinx* designers who are familiar with the Xilinx* Vivado* software and want to convert existing Vivado* designs to the Intel® Quartus® Prime Pro Edition software environment.

This application note starts with a description of the current Xilinx* and Intel® FPGA technologies and compares devices available for three different process technologies. It further highlights unique features of Intel® Agilex™ , Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices supported in the latest edition of the Intel® Quartus® Prime Pro Edition software.

The next chapter draws a parallel between the design flows in the Intel® Quartus® Prime Pro Edition software and Xilinx* Vivado* software, comparing features whenever possible.

The following chapter provides guidelines to convert Vivado* designs to the Intel® Quartus® Prime Pro Edition software, including Xilinx* IP Catalog modules and instantiated primitives. The last part of the chapter demonstrates how to translate device and design constraints.

This application note uses the latest information available for the Intel® Quartus® Prime Pro Edition software version 21.3 and Xilinx* Vivado* Design Suite version 2020.2, supporting the latest programmable chips.

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