Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

D.1. Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide Revision History

Date

Version

Changes Made

2020.03.19 17.1 Updated the reset sequence and descriptions in Reset and Clocks to show that reset_status is the output that can be used to reset the Application Layer logic.
2017.11.06 17.1 Made the following changes to the user guide.
  • Corrected Feature Comparison for all Hard IP for PCI Express IP Core table: The Avalon-MM interface does not automatically handle out-of-order completions.
2017.05.21 17.0 Made the following changes:
  • Corrected support for Completion with Data (CplD) in TLP Support Comparison for all Hard IP for PCI Express IP Cores. The Avalon-MM interface supports this TLP type.
  • Corrected default values for the Uncorrectable Internal Error Mask Register and Correctable Internal Error Mask Register registers.
  • Revised discussion of Application Layer Interrupt Handler Module to include legacy interrupt generation.

  • Added Configuration Space Register Access topic which shows the data that is multiplexed on the tl_cfg_ctl bus.

2017.05.08 16.1 Made the following changes:
  • Corrected description of the figure entitled, Cyclone V GX/GT/ST/ST Devices with 9 or 12 Transceiver Channels and 2 PCIe Cores.
2016.10.31 16.1 Made the following changes:
  • Added topic explaining how to switch between serial and PIPE simulations.
  • Corrected the number of tags supported in the Feature Comparison for all Hard IP for PCI Express IP Cores table.
  • Added PCIe bifurcation to the Feature Comparison for all Hard IP for PCI Express IP Cores table. PCI bifurcation is not supported.
  • Corrected description and timing diagram for the tl_cfg* interface in the Configuration Space Register Access Timing topic.
  • Added instructions for turning on autonomous mode in the Quartus Prime software.
2016.05.01 16.0 Made the following changes:
  • Clarified optimal read request size for typical systems that include the Avalon-MM TX slave interface.
  • Added figure for TX 3-dword header with qword aligned data
  • Corrected minor errors and typos.
2015.11.30 15.1 Made the following changes to the user guide:
  • Added TX_FIFO_EMPTY bit to the PCI Express to Avalon-MM Interrupt Status register for Legacy Endpoints only. This bit is set when the TX internal buffer is ready.
  • Enhanced the descriptions in Avalon-MM-to-PCI Express Address Translation Table.
  • Enhanced the definition of npor.
  • Added definition of Address width of accessible PCIe memory space in Parameter Settings chapter.
  • Added description of the Altera PCIe Reconfig Driver in the Connecting the Transceiver Reconfiguration Controller IP Core topic.
  • Clarified Application Layer requirements for multiple and single MSI and MSI-X support.
  • Corrected width of AVL_IRQ. It is 16 bits.
  • Added the following restriction for 128-bit Avalon-MM bridge. Supported patterns for byte enables must be at the dword granularity.
  • Clarified Avalon-MM addressing for various data widths.
  • Added signal definition for tl_cfg_ctl which was missing.
  • Removed the dlup signal. This signal is no longer part of the Hard IP Status interface.
  • Added note explaining that the Getting Started design examples do not generate all the files necessary to download to an Altera FPGA Development Kit. Provided link to AN456 PCI Express High Performance Reference Design that includes all necessary files.
2014.12.15 14.1 Made the following changes to the user guide:
  • In the figured titled Specifying the Number of Transceiver Interfaces for Arria V and Cyclone V Devices, removed the Calibrate duty cycle during power up. Duty cycle calibration occurs during Gen1 to Gen2 speed changes. This is no longer a parameter than you can turn on and off.
  • Corrected discussion of soft and hard reset controllers. The hardened reset controller is used for Arria V and Cyclone V devices.
  • Restricted Recommended Speed Grades for Cyclone V devices to GT parts for both the Gen1 and Gen2 data rates.
  • Added statement that the bottom left hard IP block includes the CvP functionality for flip chip packages. For other package types, the CvP functionality is in the bottom right block.
  • Corrected bit definitions for CvP Status register.
  • Updated definition of CVP_NUMCLKS in the CvP Mode Control register.
  • Added definitions for test_in[2], test_in[6] and test_in[7].
  • Removed requirement that TxsWrite_i be asserted continuously throughout a write burst. TxsWrite_i may be deasserted and reasserted during a burst.
  • Added figure showing connectivity for the Transceiver Reconfiguration Controller and Altera PCIe Reconfig Driver IP Cores to the Getting Started chapter.
  • Removed Maximum and High settings from the RX Buffer credit allocation -performance for received requests setting. These settings are not available for the Avalon-MM interface and could lead to data corruption.
  • Revised Receiving a Completion TLP under Programming Model for Avalon-MM Root Port to cover read and non-posted completions.
2014.06.30 14.0

Added the following features to the Cyclone V Avalon-MM Hard IP for PCI Express:

  • Added access to selected Configuration Space registers and link status registers through the optional Control Register Access (CRA) Avalon-MM slave port.
  • Added optional hard IP status bus that includes signals necessary to connect the Transceiver Reconfiguration Controller IP Core.
  • Added optional hard IP status extension bus which includes signals that are useful for debugging, including: link training, status, error, and Configuration Space signals.
  • For TxsByteEnable_i[<w>-1:0], added restrictions on the legal patterns of enabled and disabled bytes.
  • Clarified the behavior of the TxsWaitrequest_o signal.

Made the following changes to the user guide:

  • Created separate user guides for variants using the Avalon-MM, Avalon-ST, and Avalon-MM with DMA interfaces to the Application Layer.
  • Corrected frequency range for hip_reconfig_clk. It should be 100-125 MHz.
  • Simplified the Getting Started chapter. It copies the Gen1 x4 example from the install directory and does not include step-by-step instructions to recreate the design.
  • Added Next Steps in Creating a Design for PCI Express to Datasheet chapter.
  • Removed references to the MegaWizard® Plug-In Manager. In 14.0 the IP Parameter Editor Powered by Qsys has replaced the MegaWizard Plug-In Manager.
  • Corrected channel placement diagrams for Cyclone V Devices .
  • Added definition for test_in[6] and link to Knowledge Base Solution on observing the PIPE interface signals on the test_out bus.
  • Clarified that the Avalon-MM Bridge does not generate out-of-order Avalon-MM-to-PCI Express Read Completions even to different BARs.
  • Removed reconfig_busy port from connect between PHY IP Core for PCI Express and the Transceiver Reconfiguration Controller in the Altera Transceiver Reconfiguration Controller Connectivity figure. The Transceiver Reconfiguration Controller drives reconfig_busy port to the Altera PCIe Reconfig Driver.
  • Updated Recommended Speed Grades table for the Gen2 data rate. For Cyclone V devices, the Gen2 data rate requires a Cyclone V GT device. GT devices are available only for the –7 speed grade.
  • Added fact that DCD calibration is required for Gen2 data rate in the description of the transceiver reconfiguration signals. Updated figure showing Transceiver Reconfiguration Controller parameter editor.
  • Removed reference to Gen2 x1 62.5 MHz configuration in Application Layer Clock Frequency for All Combination of Link Width, Data Rate and Application Layer Interface Widths table. This configuration is not supported.
  • Added description of TxsWaitRequest signal which is asserted when the Avalon-MM bridge has eight outstanding read requests.
  • Added sections on making analog QSF and pin assignments.
  • Enhanced definition of Device ID and Sub-system Vendor ID to say that these registers are only valid in the Type 0 (Endpoint) Configuration Space.
  • Improved figure showing multiple MSI and MSI-X support and added reference to example on Altera wiki.
  • Removed references to the ATX PLL. This PLL is not available for Cyclone V
  • Updated Power Supply Voltage Requirements table.
  • Revised Physical Placement of Hard IP in Cyclone V Devices figures.
  • For Cyclone V devices changed speed grade recommendation to use GT devices for both the Gen1 and Gen2 data rate.
2014.12.20 13.1 Made the following changes:
  • Added constraints for refclk when CvP is enabled.
  • Corrected location information for nPERSTL*.
  • Corrected definition of test_in[4:1].
  • In Debugging chapter, under changing between soft and hard reset controller, changed the file name in which the parameter hip_hard_reset_hwtclmust be set to 0 to use the soft reset controller.
  • Added explanation of channel labeling for serial data. The Hard IP on the left side of the device must connect to the appropriate channels on the left side of the device, and so on.
  • Corrected connection for the Transceiver Reconfiguration Controller IP Core reset signal, alt_xcvr_reconfig_0 mgmt_rst_reset, Getting Started with the Avalon-MM Arria V Hard IP for PCI Express. This reset input connects to clk_0 clk_reset.
  • Added definition of nreset_status for variants using the Avalon-MM interface.
  • In Transaction Layer Routing Rules and Programming Model for Avalon-MM Root Port , added the fact that Type 0 Configuration Requests sent to the Root Port are not filtered by the device number. Application Layer software must filter out requests for device number greater than 0.
  • Added Recommended Reset Sequence to Avoid Link Training Issues to the Debugging chapter.
  • Added limitation for RxmIrq_<n>_i[<m>:0] when interrupts are received on consecutive cycles.
  • Updated timing diagram for tl_cfg_ctl.
  • Removed I/O Read Request and I/O Write Requests from TLPs supported for Avalon-MM interface.
  • Added note that the LTSSM interface can be used for SignalTap debugging.
  • Added restriction on the use of dynamic transceiver reconfiguration when CvP is enabled.

2014.05.06

13.0

Made the following changes:
  • Timing models are now final.
  • Added instructions for running the Single Dword variant.
  • Corrected definition of test_in[4:1]. This vector must be set to 4’b0100.
  • Corrected connection for mgmt_clk_clk in Figure 3-2.
  • Corrected definition of nPERSTL*. The device has 1 nPERSTL* pin for each instance of the Hard IP for PCI Express in the device.
  • Corrected feature comparison table in Datasheet chapter. The Avalon-MM Hard IP for PCI Express IP Core does not support legacy endpoints.

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