Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

5.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports

The Root Port supports MSI, MSI‑X and legacy (INTx) interrupts. MSI and MSI‑X interrupts are memory writes from the Endpoint to the Root Port. MSI and MSI‑X requests are forwarded to the interconnect without asserting CraIrq_o.

Table 58.   Avalon‑MM Interrupt Status Registers for Root Ports, 0x3060

Bits

Name

Access Mode

Description

[31:5]

Reserved

[4]

RPRX_CPL_RECEIVED

RW1C

Set to 1’b1 when the Root Port has received a Completion TLP for an outstanding Non-Posted request from the TLP Direct channel.

[3]

INTD_RECEIVED

RW1C

The Root Port has received INTD from the Endpoint.

[2]

INTC_RECEIVED

RW1C

The Root Port has received INTC from the Endpoint.

[1]

INTB_RECEIVED

RW1C

The Root Port has received INTB from the Endpoint.

[0]

INTA_RECEIVED

RW1C

The Root Port has received INTA from the Endpoint.

Table 59.  INT‑X Interrupt Enable Register for Root Ports, 0x3070

Bit

Name

Access Mode

Description

[31:5]

Reserved

[4]

RPRX_CPL_RECEIVED

RW

When set to 1’b1, enables the assertion of CraIrq_o when the Root Port Interrupt Status register RPRX_CPL_RECEIVED bit indicates it has received a Completion for a Non‑Posted request from the TLP Direct channel.

[3]

INTD_RECEIVED_ENA

RW

When set to 1’b1, enables the assertion of CraIrq_o when the Root Port Interrupt Status register INTD_RECEIVED bit indicates it has received INTD.

[2]

INTC_RECEIVED_ENA

RW

When set to 1’b1, enables the assertion of CraIrq_o when the Root Port Interrupt Status register INTC_RECEIVED bit indicates it has received INTC.

[1]

INTB_RECEIVED_ENA

RW

When set to 1’b1, enables the assertion of CraIrq_o when the Root Port Interrupt Status register INTB_RECEIVED bit indicates it has received INTB.

[0]

INTA_RECEIVED_ENA

RW

When set to 1’b1, enables the assertion of CraIrq_o when the Root Port Interrupt Status register INTA_RECEIVED bit indicates it has received INTA.

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