Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers

These registers contain the status of various signals in the PCI Express Avalon-MM bridge logic. These registers allow MSI or legacy interrupts to be asserted when enabled.

Only Root Complexes should access these registers; however, hardware does not prevent other Avalon-MM masters from accessing them.

Table 46.  Avalon-MM to PCI Express Interrupt Status Register, 0x0060

Bit

Name

Access

Description

[31:24]

Reserved

N/A

N/A

[23]

A2P_MAILBOX_INT7

RW1C

Set to 1 when the A2P_MAILBOX7 register is written to

[22]

A2P_MAILBOX_INT6

RW1C

1 when the A2P_MAILBOX6 register is written to

[21]

A2P_MAILBOX_INT5

RW1C

Set 10 1 when the A2P_MAILBOX5 register is written to

[20]

A2P_MAILBOX_INT4

RW1C

Set 10 1 when the A2P_MAILBOX4 register is written to

[19]

A2P_MAILBOX_INT3

RW1C

Set 10 1 when the A2P_MAILBOX3 register is written to

[18]

A2P_MAILBOX_INT2

RW1C

Set 10 1 when the A2P_MAILBOX2 register is written to

[17]

A2P_MAILBOX_INT1

RW1C

Set 10 1 when the A2P_MAILBOX1 register is written to

[16]

A2P_MAILBOX_INT0

RW1C

Set 10 1 when the A2P_MAILBOX0 register is written to

[15:0]

AVL_IRQ_ASSERTED[15:0]

RO

Current value of the Avalon-MM interrupt (IRQ) input ports to the Avalon-MM RX master port:

  • 0—Avalon-MM IRQ is not being signaled.
  • 1—Avalon-MM IRQ is being signaled.

A PCIe* variant may have as many as 16 distinct IRQ input ports. Each AVL_IRQ_ASSERTED[] bit reflects the value on the corresponding IRQ input port.

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