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Ixiasoft
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Ixiasoft
1.1. Avalon-MM Interface for PCIe Datasheet
Intel® Cyclone® V FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with PCI Express Base Specification 2.1 or 3.0.
The Hard IP for PCI Express PCIe* IP core using the Avalon® Memory-Mapped (Avalon-MM) interface removes some of the complexities associated with the PCIe protocol. For example, it handles all of the Transaction Layer Protocol (TLP) encoding and decoding. Consequently, you can complete your design more quickly. The Avalon-MM interface is implemented as a bridge in FPGA soft logic. It is available in Qsys. The following figure shows the high-level modules and connecting interfaces for this variant.
Link Width in Gigabits Per Second (Gbps) | |||
---|---|---|---|
×1 | ×2 | ×4 | |
PCI Express Gen1 (2.5 Gbps) |
2 |
4 |
8 |
PCI Express Gen2 (5.0 Gbps) |
4 |
8 |
16 |
Refer to the PCI Express High Performance Reference Design for more information about calculating bandwidth for the hard IP implementation of PCI Express in many Intel FPGAs.