Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

1.8. Performance and Resource Utilization

Because the PCIe protocol stack is implemented in hardened logic, it uses less than 1% of device resources.

The Avalon-MM bridge is implemented in soft logic and functions as a front end to the hardened protocol stack. The following table shows the typical device resource utilization for selected configurations using the current version of the Quartus® Prime software. With the exception of M10K memory blocks, the numbers of ALMs and logic registers in the following tables are rounded up to the nearest 50.

Table 6.  Performance and Resource Utilization Avalon-MM Hard IP for PCI Express

Data Rate or Interface Width

ALMs

Memory M10K

Logic Registers

Avalon‑MM Bridge

Gen1 ×4

1250

27

1700

Avalon-MM Interface–Completer Only

64

600

11

900

128

1350

22

2300

Avalon-MM–Completer Only Single DWord

64

160

0

230

Note: Soft calibration of the transceiver module requires additional logic. The amount of logic required depends on the configuration.

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