Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

Clock Summary

Name

Frequency

Clock Domain

coreclkout_hip

62.5, 125 or 250 MHz

Avalon‑ST interface between the Transaction and Application Layers.

pld_clk

pld_clk has a maximum frequency of 250 MHz and a minimum frequency that can be equal or more than the coreclkout_hip frequency, depending on the link width, link rate, and Avalon® interface width as indicated in the table for the Application Layer clock frequency above.

Application and Transaction Layers.

refclk

100 or 125 MHz

SERDES (transceiver). Dedicated free running input clock to the SERDES block.

reconfig_xcvr_clk

100 –125 MHz

Transceiver Reconfiguration Controller.

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