Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

5.8.5. Root Port TLP Data Registers

The TLP data registers provide a mechanism for the Application Layer to specify data that the Root Port uses to construct Configuration TLPs, I/O TLPs, and single dword Memory Reads and Write requests. The Root Port then drives the TLPs on the TLP Direct Channel to access the Configuration Space, I/O space, or Endpoint memory.

Figure 27. Root Port TLP Data Registers
Note: The high performance TLPs implemented by Avalon‑MM ports in the Avalon‑MM Bridge are also available for Root Ports. For more information about these TLPs, refer to Avalon-MM Bridge TLPs.
Table 60.  Root Port TLP Data Registers, 0x2000–0x2FFF

Root-Port Request Registers

Address Range: 0x2800-0x2018

Address

Bits

Name

Access

Description

0x2000

[31:0]

RP_TX_REG0

W

Lower 32 bits of the TX TLP.

0x2004

[31:0]

RP_TX_REG1

W

Upper 32 bits of the TX TLP.

0x2008

[31:2]

Reserved

[1]

RP_TX_CNTRL.EOP

W

Write 1’b1 to specify the of end a packet. Writing this bit frees the corresponding entry in the FIFO.

[0]

RP_TX_CNTRL.SOP

W

Write 1’b1 to specify the start of a packet.

Note: Both bits [1] and [0] are equal to 0 for all cycles in the packet except for the SOP and EOP cycles.

0x2010

[31:2]

Reserved

 

[1]

RP_RXCPL_STATUS.EOP

R

When 1’b1, indicates that the final data for a Completion TLP is ready to be read by the Application Layer. The Application Layer must poll this bit to determine when the final data for a Completion TLP is available.

 

[0]

RP_RXCPL_STATUS.SOP

R

When 1’b1, indicates that the data for a Completion TLP is ready to be read by the Application Layer. The Application Layer must poll this bit to determine when a Completion TLP is available.

0x2014

[31:0]

RP_RXCPL_REG0

RC

Lower 32 bits of a Completion TLP. Reading frees this entry in the FIFO.

0x2018

[31:0]

RP_RXCPL_REG1

RC

Upper 32 bits of a Completion TLP. Reading frees this entry in the FIFO.

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