Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port

Table 57.  Configuration Space Register Descriptions For registers that are less than 32 bits, the upper bits are unused.
Byte Offset

Register

Dir

Description

14'h3C00 cfg_dev_ctrl[15:0]

O

cfg_devctrl[15:0] is device control for the PCI Express capability structure.

14'h3C04 cfg_dev_ctrl2[15:0]

O

cfg_dev2ctrl[15:0] is device control 2 for the PCI Express capability structure.

14'h3C08 cfg_link_ctrl[15:0]

O

cfg_link_ctrl[15:0]is the primary Link Control of the PCI Express capability structure.

For Gen2 or Gen3 operation, you must write a 1’b1 to Retrain Link bit (Bit[5] of the cfg_link_ctrl) of the Root Port to initiate retraining to a higher data rate after the initial link training to Gen1 L0 state. Retraining directs the LTSSM to the Recovery state. Retraining to a higher data rate is not automatic for the Cyclone V Hard IP for PCI Express IP Core even if both devices on the link are capable of a higher data rate.

14'h3C0C cfg_link_ctrl2[15:0]

O

cfg_link_ctrl2[31:16] is the secondary Link Control register of the PCI Express capability structure for Gen2 operation.

For Gen1 variants, the link bandwidth notification bit is always set to 0. For Gen2 variants, this bit is set to 1.

14'h3C10 cfg_prm_cmd[15:0]

O

Base/Primary Command register for the PCI Configuration Space.

14'h3C14 cfg_root_ctrl[7:0]

O

Root control and status register of the PCI-Express capability. This register is only available in Root Port mode.

14'h3C18 cfg_sec_ctrl[15:0]

O

Secondary bus Control and Status register of the PCI-Express capability. This register is only available in Root Port mode.

14'h3C1C cfg_secbus[7:0]

O

Secondary bus number. Available in Root Port mode.

14'h3C20 cfg_subbus[7:0]

O

Subordinate bus number. Available in Root Port mode.

14'h3C24 cfg_msi_addr_low[31:0]

O

cfg_msi_add[31:0] is the MSI message address.

14'h3C28 cfg_msi_addr_hi[63:32]

O

cfg_msi_add[63:32] is the MSI upper message address.

14'h3C2C cfg_io_bas[19:0]

O

The IO base register of the Type1 Configuration Space. This register is only available in Root Port mode.

14'h3C30 cfg_io_lim[19:0]

O

The IO limit register of the Type1 Configuration Space. This register is only available in Root Port mode.

14'h3C34 cfg_np_bas[11:0]

O

The non-prefetchable memory base register of the Type1 Configuration Space. This register is only available in Root Port mode.

14'h3C38 cfg_np_lim[11:0]

O

The non-prefetchable memory limit register of the Type1 Configuration Space. This register is only available in Root Port mode.

14'h3C3C cfg_pr_bas_low[31:0]

O

The lower 32 bits of the prefetchable base register of the Type1 Configuration Space. This register is only available in Root Port mode.

14'h3C40 cfg_pr_bas_hi[43:32]

O

The upper 12 bits of the prefetchable base registers of the Type1 Configuration Space. This register is only available in Root Port mode.

14'h3C44 cfg_pr_lim_low[31:0]

O

The lower 32 bits of the prefetchable limit registers of the Type1 Configuration Space. Available in Root Port mode.

14'h3C48 cfg_pr_lim_hi[43:32]

O

The upper 12 bits of the prefetchable limit registers of the Type1 Configuration Space. Available in Root Port mode.

14'h3C4C cfg_pmcsr[31:0]

O

cfg_pmcsr[31:16] is Power Management Control and cfg_pmcsr[15:0]is the Power Management Status register.

14'h3C50 cfg_msixcsr[15:0]

O

MSI-X message control register.

14'h3C54 cfg_msicsr[15:0]

O

MSI message control.

14'h3C58 cfg_tcvcmap[23:0]

O

Configuration traffic class (TC)/virtual channel (VC) mapping. The Application Layer uses this signal to generate a TLP mapped to the appropriate channel based on the traffic class of the packet.

The following encodings are defined:
  • cfg_tcvcmap[2:0]: Mapping for TC0 (always 0).
  • cfg_tcvcmap[5:3]: Mapping for TC1.
  • cfg_tcvcmap[8:6]: Mapping for TC2.
  • cfg_tcvcmap[11:9]: Mapping for TC3.
  • cfg_tcvcmap[14:12]: Mapping for TC4.
  • cfg_tcvcmap[17:15]: Mapping for TC5.
  • cfg_tcvcmap[20:18]: Mapping for TC6.
  • cfg_tcvcmap[23:21]: Mapping for TC7.
14'h3C5C cfg_msi_data[15:0]

O

cfg_msi_data[15:0] is message data for MSI.

14'h3C60 cfg_busdev[12:0]

O

Bus/Device Number captured by or programmed in the Hard IP.

14'h3C64 ltssm_reg[4:0]

O

Specifies the current LTSSM state. The LTSSM state machine encoding defines the following states:
  • 00000: Detect.Quiet
  • 00001: Detect.Active
  • 00010: Polling.Active
  • 00011: Polling.Compliance
  • 00100: Polling.Configuration
  • 00101: Polling.Speed
  • 00110: config.Linkwidthstart
  • 00111: Config.Linkaccept
  • 01000: Config.Lanenumaccept
  • 01001: Config.Lanenumwait
  • 01010: Config.Complete
  • 01011: Config.Idle
  • 01100: Recovery.Rcvlock
  • 01101: Recovery.Rcvconfig
  • 01110: Recovery.Idle
  • 01111: L0
  • 10000: Disable
  • 10001: Loopback.Entry
  • 10010: Loopback.Active
  • 10011: Loopback.Exit
  • 10100: Hot.Reset
  • 10101: LOs
  • 11001: L2.transmit.Wake
  • 11010: Recovery.Speed
  • 11011: Recovery.Equalization, Phase 0
  • 11100: Recovery.Equalization, Phase 1
  • 11101: Recovery.Equalization, Phase 2
  • 11110: recovery.Equalization, Phase 3
14'h3C68 current_speed_reg[1:0]

O

Indicates the current speed of the PCIe link. The following encodings are defined:

  • 2b’00: Undefined
  • 2b’01: Gen1
  • 2b’10: Gen2
  • 2b’11: Gen3
14'h3C6C lane_act_reg[3:0]

O

Lane Active Mode: This signal indicates the number of lanes that configured during link training. The following encodings are defined:

  • 4’b0001: 1 lane
  • 4’b0010: 2 lanes
  • 4’b0100: 4 lanes
  • 4’b1000: 8 lanes

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